Which technique resolves data hazards in a classic CPU instruction pipeline?

• A. Branch Prediction
• B. Software caching
• C. Forwarding
• D. Interrupt masking

Answer: (C)

Data hazards in a classic CPU instruction pipeline occur when an instruction depends on the result of a previous instruction that hasn’t been written back yet. Forwarding, also called bypassing, resolves these hazards by feeding the result directly from the stage where it’s produced to the stage where it’s needed, bypassing the register file. For example, if an ADD computes a value in the EX stage and the next instruction needs that value in its own EX stage, the hardware can route the produced result from the producing path (such as the EX/MEM latch) into the input of the next instruction’s ALU. This lets the second instruction proceed without waiting for the first to complete a write-back, significantly reducing stalls in a typical five-stage pipeline. Branch prediction is about control hazards caused by branches, interrupt masking deals with asynchronous interruptions, and software caching isn’t a pipeline hazard-resolution technique, so they don’t address data hazards like forwarding does.