Which statement correctly describes address aliasing, cache coherence, and TLB considerations in a system with virtual memory?

• A. Aliasing occurs when a single physical address maps to multiple virtual addresses; this is why TLBs are unnecessary.
• B. TLB coherence is not necessary if caches are inclusive.
• C. Aliasing occurs when different virtual addresses map to the same physical address; TLB coherence and page table consistency ensure correct mappings across cores.
• D. Caches are not affected by virtual memory addressing.

Answer: (C)

In memory systems with virtual addressing, multiple virtual addresses can end up pointing to the same physical page. That situation is aliasing: different virtual addresses mapping to one physical address. Because the Translation Lookaside Buffer caches virtual-to-physical translations and because there are multiple cores with their own caches, the page-table mappings must stay synchronized across all cores. If a page-table entry changes (for example, a page is moved, permissions are updated, or a page is swapped), every core must see that change; otherwise a core might use an outdated translation and access the wrong data. This is why TLB coherence and page-table consistency are essential for correct operation across cores.

The statement highlights that aliasing can occur and that maintaining coherence of the TLBs and the page tables across cores is what keeps translations correct. The other options are not accurate: TLBs are still needed for fast translation, and cache behavior alone doesn’t protect correctness when page-table mappings change; virtual memory affects how data is cached because the physical address used by the cache depends on the translation.