Which of the following best describes the purpose of the Translation Lookaside Buffer (TLB) in memory management?

• A. Total Load Buffer
• B. Time Latency Buffer
• C. Translation Lookaside Buffer; caches recent virtual-to-physical address translations.
• D. Memory protection key

Answer: (C)

A Translation Lookaside Buffer speeds memory access by caching recent virtual-to-physical address translations, so the processor doesn’t have to walk the page table for every memory reference.

When the CPU needs to access a memory location, it must translate the virtual address to a physical frame number. Doing this by repeatedly reading the page table from memory is slow, especially since page tables can be multi-level. The TLB sits between the CPU and memory and stores a small number of these translations. If the needed mapping is in the TLB (a hit), the physical address is obtained quickly and the access proceeds. If it’s not in the TLB (a miss), the system must fetch the translation from the page table in memory, possibly perform a multi-level walk, and then refill the TLB with the new translation for future accesses. This cache of translations dramatically reduces latency for programs with locality, which is why virtual memory performance hinges on a well-functioning TLB.

The other options don’t describe this mechanism. They refer to concepts that aren’t involved in translating virtual addresses to physical addresses or are unrelated features.