How do NVMe devices achieve high throughput on PCIe?

• A. They use a single PCIe lane only.
• B. They use many queues and parallelism within PCIe.
• C. They rely on the CPU cache exclusively.
• D. They use the SCSI protocol.

Answer: (B)

NVMe achieves high throughput on PCIe by exploiting deep parallelism in both the transport and the command interface. PCIe provides multiple lanes that can carry data concurrently, offering high aggregate bandwidth. NVMe takes advantage of this by using a very large number of I/O queues and a high queue depth, which lets thousands of commands be in flight at once. With many submission and completion queues, the controller can keep the PCIe data paths busy, hiding latency and sustaining high transfer rates as operations overlap. This combination—massive parallelism through queues and the parallel data paths of PCIe—is what enables NVMe to outperform alternatives that rely on fewer concurrent operations. Using a single PCIe lane would bottleneck bandwidth, CPU caches aren’t a scalable mechanism for sustained throughput, and the SCSI protocol is not used by NVMe.