Describe the cache memory hierarchy and the MESI cache coherence protocol used in multi-core systems.

• A. The cache hierarchy consists of L1, L2, and L3 caches between the CPU and memory.
• B. Modified, Exclusive, Shared, Invalid; coherence ensures all cores see consistent data; transitions handle writes and cache lines.
• C. MESI states are Modified, External, Shared, Internal.
• D. Cache coherence is unnecessary in multi-core systems.

Answer: (B)

Understanding how multiple caches stay in sync is essential when designing or analyzing multi-core systems, and this hinges on how data moves through the cache hierarchy and how coherence is maintained. The MESI protocol manages the state of each cached line to coordinate access across cores, keeping everything consistent.

The key states are Modified, Exclusive, Shared, and Invalid. Modified means the cache line has been written to and is dirty; it is the only copy and memory has stale data, so a write-back is needed when evicted. Exclusive means the line is clean (matches memory) and is the only copy in any cache. Shared means the line is clean and may be present in multiple caches, allowing concurrent reads by different cores. Invalid means the line in that cache is no longer valid for use.

Coherence ensures all cores see the same value by controlling transitions when lines are read or written. A read miss brings the line into a valid state, often as Exclusive or Shared depending on whether other caches already hold it. A write typically requires upgrading to Modified and invalidating or updating copies in other caches. When a line is evicted, a dirty Modified copy is written back to memory.

This answer is the best because it accurately names the four MESI states and succinctly explains how coherence maintains consistency across cores through the state transitions of cache lines. Other statements either misname the states or omit the coherence aspect entirely.